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Before You Start – System Requirements
To run all features Organic Process Design Kit (OPDK) in Cadence, please first make sure you have met the following system requirement:
1. Cadence Virtuoso, version 6.1.1 or higher.
2. Mentor Calibre 2006.4 (OA 2.2.5) or higher
Running OPDK with a lower version of Cadence or Mentor is not tested and may require changes in configuration. If you are not sure about your system environment, please contact your IT support.
1.1 Make a new directory called OPDK under your home directory:
mkdir OPDK
1.2 Go to OPDK:
cd OPDK
1.3 Copy the file OPDK-1.2.tar to directory OPDK by using the command from this directory:
cp OPDK-1.5.tar.gz .
1.4 Extract the archive using the command
tar -zxvf OPDK-1.5.tar.gz
1.5 You should now be able to see the extracted files under OPDK at your home directory. This contains an open-source, open-access based OPDK for organic electronic applications based on ion-gel technology from the Department of CEMS at the University of Minnesota, Twin Cities.
1.6 Go to organic_basekit/cdssetup under OPDK directory
cd organic_basekit/cdssetup
Here, you will have to modify setup.csh using vi, nano or any of your favorite editors as follows:
1.6.1 Comment out the line which defines the environment variable OPDK_DIR (it starts with "setenv”).
Lines can be commented out by adding a # at the beginning.
1.6.2 Set the OPDK_DIR variable to the root directory of the OPDK distribution
setenv OPDK_DIR <your_absolute_local_path>/OPDK
1.6.3 Comment out the line which defines the environment variable CDSHOME.
1.6.4 Set the CDSHOME variable to the root directory the Cadence installation. For example:
setenv CDSHOME /home/apps/common/cadence/Linux/ ic_611/tools.lnx86/
1.6.5 Save and exit the file. Your OPDK is setup and ready to be used now.
1.7 Create your temporary Cadence work directory at OPDK
cd OPDK/
mkdir cds
cd cds
Always run Cadence from this directory to avoid cluttering up your workspace.
1.8 Copy setup.csh (the file you modified in step 1.6) into this directory
cp ../organic_basekit/cdssetup/setup.csh .
Source this script using the following command
source setup.csh
This script copies the files needed by Cadence and initializes the environment.
1.9 Invoke Cadence by typing:
virtuoso &
This should bring up the command interface window and library manager. You are now ready to design circuits in Cadence.
2. Example: Design of an Inverter with Top-Gated P3HT-Channel TFT
This example will help you familiarize yourself with OPDK in Cadence. This will show the most important commands and steps used when working with schematics in Cadence. As an example, you will design a simple inverter with resistor load. For details of the various components, please refer to the next few chapters.
Before starting with the design example, there are a couple things worth mentioning:
· Most of the commands in Cadence can be accessed in multiple ways: pull-down menus, shortcut keys, buttons in toolbars, etc. In the described example, all the commands are referenced by their position in the pull-down menus. The shortcut keys can be found from the pull-down menus as well.
· The most frequently used key in Cadence is ESC. It is used to cancel on-going commands.
The following picture shows the schematic of an inverter, which is ready for netlist extraction. The following section explains how to draw it in Cadence.
2.1 Create a library for your new design
From the library manager window:
File->New->Library
Type a new name, such as TEST, click OK.
In
the pop-up window, choose “Attach
to an existing tech library”.
Then, choose “OPDK_TechLib”).
Click OK.
2.2 Create a new cell
In the Library Manager, highlight your new library (TEST if that is what you chose).
File->New->Cellview
Choose library TEST, cell name “inverter”, view name “schematic”, and Open with “Schematic L”. Click OK.
Click “Always” if “Upgrade License” warning message shows up.
A schematic window will open.
2.3 Design your circuit
2.3.1 Place components
For this inverter, you will need a top-gated P3HT-channel TFT and a resistor.
From Schematic window,
Create->Instance
Add Instance and Library Browser windows will open. If the Library Browser window does not open automatically, simply click Browse on the Add Instance window. Make sure the Library in the Library Browser is set to OPDK_Devices. Use the LibraryBrowser window and click on PTFT_P3HT_TG, then select symbol and close the window.
In the Add Instance window, type in the appropriate width and length values. Here we use width= 500um and length=50um. Place the PTFT in the schematic window.
Similarly, place a resistor of 10K Ohm with the “res” symbol.
If you make any mistake, you can always use:
Edit->Delete
or
Edit->Rotate or
Edit->Move or
Edit->Stretch
To change the properties of some of the components:
Edit->Properties->Objects
2.3.2 Place pins
For this inverter, you will need five pins: ground (GND), negative power (VDDN), input (IN), output (OUT) and substrate (SUB).
From Schematic window,
Create->Pin
Add Pin window will open. Type in the pin names and place the pins in the appropriate locations. Pay attention to the red box shown below, and make sure you choose the right I/O direction for each pin. For example, IN should be Input, OUT should be Output, and all the rest should be InputOutput.
2.3.3 Connect components
Connect the component terminals as shown in the figure above using:
Create->Wire (narrow)
2.4 Generate netlist files
In the Schematic Window:
Design->Check and Save
There should be no errors. Then go Launch->ADE L.
The window
of Cadence Analog Design Environment will
show up.
Make
sure the current simulator is set to hspiceD:
Setup->Simulator/Directory/Host
Set the simulator to hspiceD.
Simulation->Netlist->Create
A new window will pop up showing the generated HSPICE netlist. You may save this file by clicking the menu bar:
File->Save As
Specify the full path name and file name in the Save As window. If you have models ready, you can use this netlist file to run simulations with the model. You may need to modify some of the netlist, which we will not discuss in details.
2.5 Working with symbols
If you want to use your design in other schematics, you need to create a symbol for it. This is equivalent to the use of sub-circuits in HSPICE. Using hierarchy in your project makes it easier to organize.
2.5.1 Create a new symbol
Save the schematic before you create its symbol:
File->Check and Save
Create->Cellview->From Cellview, click OK.
A new window will open with the symbol view. By default, the symbol shape is a rectangle, but you can change it. Since this design is an inverter, we will draw a triangle and put a small circle at the output. To do this, you will want to delete the green rectangle, draw the new shape, and move the terminals to new positions. Use Create->Shape to draw a triangle and place a circle. There are several shapes available: line, rectangle, circle, etc.
You will also need to change the Selection box (the red rectangle), which defines the limits of the symbol. This can be done bystretching the Selection box. Figure below shows an example of the inverter symbol:
Don't forget to check and save.
2.5.2 Use the symbol in other schematics
Create a new schematic, using the instructions described in Create a new cell. Give a name such as test_inverter.
You place this symbol in the new schematic in the same way that you placed any other components, with:
Create->Instance
This time change the Library to your library TEST and click on inverter. Your symbol should be here.
To move in the hierarchy, select the inverter, and then:
Edit->Hierarchy->Descend Edit.
You can choose the schematic or the symbol for editing.
To return to the previous schematic, use:
Edit->Hierarchy->Return
3. Example: Layout of an Inverter with Top-Gated P3HT-Channel TFT
This example will help you to create a layout for the inverter you designed in the first example. The following picture shows a layout for the inverter. The following sections explain how to make each of the separate components in Virtuoso.
3.1 Create a layout view of your cell
In the Library Manager, Highlight your inverter schematic library (TEST if that is what you chose).
File -> New -> Cellview
Change the view type to layout and open with layout L. Click OK. Click “Always” if there is any license upgrade message.
A layout-editing and an LSW window will open up.
3.2 Layout the components for your circuit
For this inverter we will need to layout a Top-gated P3HT-channel PTFT and a resistor.
3.2.1 Layout a PTFT
For better illustration, it is recommended to draw different layers in the order of how it is actually fabricated.
A.
METAL1
In the LSW window, choose METAL1 (drw). From the Layout window, choose
Create->Shape->Rectangle
1. Draw the source/drain electrodes. Assume we are going to draw a PTFT with W/L = 500um/50um, with a source/drain electrode width of 10um. Draw a rectangle of 500um x 10um, and draw another one under the first rectangle, with 50um distance in between.
2. Draw the source/drain connections to other nets. On the right side of the drawn electrodes, draw two rectangles in METAL1, each being 100um x 200um.
3. Draw the gate electrode. On the left side of the drawn electrodes, draw a rectangle of 100um x 200um in METAL1, with 100um distance away from the source/drain electrodes.
The final pattern should look like this:
B. P3HT Channel
Select P3HT_TFT (drw) from LSW window, and draw a rectangle of 500um x 120um, covering the entire two source/drain electrodes and filling the entire 50um gap to form a channel.
C. Ion-Gel Dielectric
Select IONGEL_TFT (drw) from LSW window, and draw a rectangle of 700um x 120um, completely enclosing the P3HT channel, with 25um extension on the length direction and 50um extension on the width side onto METAL1.
D. PEDOT Conductive Layer
Select PEDOT_TFT (drw) from LSW window, and draw a rectangle of 675um x 25um, placed roughly in the middle of the channel. Locate the rectangle so that it extends onto METAL1 over Iongel layer on the gate side by 50um. Iongel layer should also enclose this PEDOT layer by 25um on the right side.
E. Contact
For LVS purpose, dummy contacts are required in layout. Select COTFT (drw) from LSW window and draw rectangles at source (P3HT overlapping METAL1) and drain (P3HT overlapping METAL1). Select CONTACT (drw) from LSW window for rectangles at gate (PEDOT overlapping METAL1 but not interacting with IONGEL).
F. Substrate
For LVS purpose, substrate layer is required in layout. Select SUB (drw) from LSW window and draw a rectangle to enclose everything.
The final layout should look like this:
3.2.2 Layout a resistor
A. METAL1
OPDK provides three types of resistor layers: PEDOT_R2K, PEDOT_R10K and PEDOT_R100K. The resistor value is calculated by L/W*R_Unit, where R_Unit value is the suffix of each type of layer.
Assume we are going to draw a 10K resistor with PEDOT_R2K. L/W ratio should be 5 according to the calculation. So here we can go with width=100um and length=500um.
Select METAL1 from LSW window, and draw two rectangles of 300um x 100um, being 500um away from each other in Y-direction.
B. Resistor
Select PEDOT_R2K (drw) from LSW window and draw a rectangle of 100um x 700um, extending onto METAL1 layers by 100um each.
C. Substrate
Select SUB (drw) from LSW window and draw a rectangle to enclose everything, or simply stretch the previous SUB.
The final layout should look like this:
3.2.3 Add pins
For LVS purpose, pins are required in layout.
Create -> Pin
A Create Pin window will open.
Type in the pin names and check “Display Pin Name”. Click “Display Pin Name Option” and a Pin Name Display window opens. Set the text height to 50, and set appropriate layer for the pins. In this example, SUB should be of SUB (drawing) layer while all the rest should be of METAL1 (drawing) layer. Do not close the windows before you finish your drawing.
Go back to the layout view, and select the appropriate layer (METAL1 drawing) in the LSW window for the first pin you will place (GND). Draw a rectangle on the metal plate of ground, and place the text on or near it. You can do the rest in the same way.
Note: Do not use “Create-Rectangle” to draw the pins. The “Create-Pin” command automatically provides rectangle drawings.
Note: Be sure to change the layer for SUB.
The final layout should be look like the one shown in the beginning of this section.
3.3 Route
If in the future you need to route between different instances or cells, simply use METAL1 for connection.
3.4 Grid control for layout
In the layout view, the mouse pointer only snaps to a certain spacing of location. The spacing can be set by:
Options->Display
In the Grid Control panel, the “X Snap Spacing” and “Y Snap Spacing” control the resolution of mouse snap in layout. In default, “X Snap Spacing” and “Y Snap Spacing” are set to 1μm. You should either keep the default setting or change them to multiples of 1um in your layout because in this design kit, DRC rule requires the edge of the drawing (e.g. rectangle wire) lies on a grid which is a multiple of 1μm.
3.4 Perform DRC Verification
It's always a good practice to stop and do a DRC check from time to time before placing more components to your diagram. To do so, clicking on:
Calibre->Run DRC...
A window that looks like the one below opens up. Set the DRC Rules File to:$OPDK_DIR/organic_basekit/techfile/calibre/calibreDRC.rul and DRC Run Directory to: $OPDK_DIR/runcalibre.
Click on Run DRC and the DRC will now run.
If everything is okay, it should finish with this popped-out window:
If there are errors, the message will contain statistics about which rules were violated. To see why and where you violate the DRC rule, double click on the error messages and the corresponding layers or boundaries will be highlighted in the layout. To understand the details of the DRC rules, please visit the website of OPDK.
3.5 Perform LVS Verification
The LVS tool is used to compare the layout with the schematic, identifying any circuit related differences that might exist between these two views. It reports circuit nodes and device sizes. It is a very useful tool since it helps us identify wrong connections or shorts or open-circuits that may be difficult to be discovered by naked eyes.
To perform LVS verification, click on:
Calibre -> Run LVS…
The LVS dialog window opens up. Again, set the LVS Rules File to: $OPDK_DIR/organic_basekit/techfile/calibre/calibreLVS.rul and LVS Run Directory to: $OPDK_DIR/runcalibre. Go to “Inputs” and make sure for both Layout and Netlist, “Export from layout (or schematic) viewer” is checked. Click on Run LVS and the LVS will now run.
If everything is okay, it should finish with this popped-out window:
If there are errors, the message will contain statistics about what kind of errors are found. To see why and where you get an error, double click on the error messages and the corresponding layers or boundaries will be highlighted in the layout.
Note: Sometimes you may have multiple labels with the same name, e.g. “GND” on a few separated GND rails. If they are eventually going to be connected, while you want to leave them separated at the moment, you should go to Setup->LVS Optionsand enable LVS Options menu, and check Connect->Connect all nets by name. This will automatically recognize all nets with the same name to be connected, even if they are not physically connected in your layout. So you need to be careful when using this option. Or you can check Connect->Connect nets named and specify the net names to be connected during LVS.